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integrated silicon solution, inc. ? 1-800-379-4774 1 preliminary information rev. 00b 05/09/01 this document contains preliminary information data. issi reserves the right to make changes to its products at any time witho ut notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2001, int egrated silicon solution, inc. is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp and 119-pin pbga package single +3.3v, +10%, ?5% power supply power-down snooze mode 3.3v i/o for sps 2.5v i/o for lps single cycle deselect snooze mode for reduced-power standby t version (three chip selects) d version (two chip selects) description the issi is61sps25632, is61sps25636, is61sps51218, is61lps25632, is61lps25636, and is61lps51218 are high-speed, low-power synchronous static rams designed to provide a burstable, high-performance memory for communication and networking applications. the is61sps25632 and is61lps25632 are organized as 262,144 words by 32 bits and the is61sps25636 and is61lps25636 are organized as 262,144 words by 36 bits. the is61sps51218 and is61lps51218 are organized as 524,288 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ).input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. 256k x 32, 256k x 36, 512k x 18 synchronous pipeline, single-cycle deselect static ram preliminary information may 2001 fast access time symbol parameter -150 -133 units t kq clock access time 3.8 4 ns t kc cycle time 6.7 7.5 ns frequency 150 133 mhz www.datasheet.in
2 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? block diagram 18/19 binary counter a17-a0 (61sps25632/36, 61lps25632/36) bwa gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bwd (t, d) ce (t) ce2 (t, d) ce2 bwb bwc 256kx32; 256kx36; 512kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 4 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a18-a0 (61sps51218, 61lps51218) (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18) www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 3 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin configuration a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 nc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 nc a5 nc nc a4 a3 a2 gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd nc a14 nc a16 a17 a15 nc dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 nc a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc a6 a7 ce ce2 bwd bwc bwb bwa a17 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 119-pin pbga (top view) 100-pin tqfp (d version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable gnd q isolated output buffer ground www.datasheet.in
4 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin configuration nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc a6 a7 ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc a17 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 100-pin tqfp (t version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable gnd q isolated output buffer ground www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 5 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin configuration a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 dqpc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 dqpd a5 nc nc a4 a3 a2 gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd nc a14 nc a16 a17 a15 dqpb dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 dqpa a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa a6 a7 ce ce2 bwd bwc bwb bwa a17 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 256k x 36 119-pin pbga (top view) 100-pin tqfp (d version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o www.datasheet.in
6 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin configuration dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa a6 a7 ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc a17 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 256k x 36 100-pin tqfp (t version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 7 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin configuration a17 nc nc vccq gnd nc dqpa dqa8 dqa7 gnd vccq dqa6 dqa5 gnd nc vcc zz dqa4 dqa3 vccq gnd dqa2 dqa1 nc nc gnd vccq nc nc nc a6 a7 ce ce2 nc nc bwb bwa a18 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc nc nc vccq gnd nc nc dqb1 dqb2 gnd vccq dqb3 dqb4 vcc vcc nc gnd dqb5 dqb6 vccq gnd dqb7 dqb8 dqpb nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 a b c d e f g h j k l m n p r t u vccq nc nc dqb1 nc vccq nc dqb4 vccq nc dqb6 vccq dqb8 nc nc nc vccq a6 ce2 a7 nc dqb2 nc dqb3 nc vcc dqb5 nc dqb7 nc dqpb a5 a11 nc a4 a3 a2 gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc nc nc a8 a9 a12 gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd nc a14 nc a16 a18 a15 dqpa nc dqa7 nc dqa5 vcc nc dqa3 nc dqa2 nc a13 a17 nc vccq nc nc nc dqa8 vccq dqa6 nc vccq dqa4 nc vccq nc dqa1 nc zz vccq 1 2 3 4 5 6 7 512k x 18 119-pin pbga (top view) 100-pin tqfp (d version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a18 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqb synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpb parity data i/o dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 www.datasheet.in
8 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a18 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqb synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpb parity data i/o dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 pin configuration a17 nc nc vccq gnd nc dqpa dqa8 dqa7 gnd vccq dqa6 dqa5 gnd nc vcc zz dqa4 dqa3 vccq gnd dqa2 dqa1 nc nc gnd vccq nc nc nc a6 a7 ce ce2 nc nc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc nc nc vccq gnd nc nc dqb1 dqb2 gnd vccq dqb3 dqb4 vcc vcc nc gnd dqb5 dqb6 vccq gnd dqb7 dqb8 dqpb nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc a18 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 512k x 18 100-pin tqfp (t version) www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 9 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? partial truth table function gw bwe bwa bwb bwc bwd read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx truth table address operation used ce ce2 ce2 adsp adsc adv write oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none l x h h l x x x high-z deselected, power-down none l l x h l x x x high-z read cycle, begin burst external l h l l xxxxq read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x w rite x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l w rite x d write cycle, continue burst next h x x x h l w rite x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst c urrent x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h x x x h h w rite x d www.datasheet.in
10 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? interleaved burst address table (mode = v cc or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias ? 40 to +85 c t stg storage temperature ? 55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ? 0.5 to v ccq + 0.5 v v in voltage relative to gnd for ? 0.5 to v cc + 0.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd ? 0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 11 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? operating range range ambient temperature v cc v ccq commercial 0 c to +70 c 3.3v, +10%, ? 5% 2.375 ? 3.6v industrial ? 40 c to +85 c 3.3v, +10%, ? 5% 2.375 ? 3.6v dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ? 2.0 ma, v ccq = 2.5v 1.7 ? v i oh = ? 4.0 ma, v ccq = 3.3v 2.4 ? v v ol output low voltage i ol = 2.0 ma, v ccq = 2.5v ? 0.7 v i ol = 8.0 ma, v ccq = 3.3v ? 0.4 v v ih input high voltage v ccq = 2.5v 1.7 v ccq + 0.3 v v ccq = 3.3v 2.0 v ccq + 0.3 v v il input low voltage v ccq = 2.5v ? 0.3 0.7 v v ccq = 3.3v ? 0.3 0.8 v i li input leakage current gnd v in v ccq (2) com. ? 22a ind. ? 55 i lo output leakage current gnd v out v ccq , oe = v ih com. ? 22a ind. ? 55 power supply characteristics (over operating range) -150 -133 symbol parameter test conditions max. max. unit i cc ac operating device selected, com. 250 230 ma supply current all inputs = v il or v ih ind. 280 250 ma oe = v ih , vcc = max. cycle time t kc min. i sb standby current device deselected, com. 50 40 ma v cc = max., ind. 60 50 ma all inputs = v ih or v il clk cycle time t kc min. notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v cc . 2. the mode pin should be tied to vcc or gnd. it exhibits 10 a maximum leakage current when tied to - gnd + 0.2v or vcc ? 0.2v. www.datasheet.in
12 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v for 3.3v i/o and reference level v ccq /2v for 2.5v i/o output load see figures 1 and 2 figure 2 317 ? /1667 ? 5 pf including jig and scope 351 ? /1538 ? output 3.3v for 3.3v i/o /2.5v for 2.5v i/o figure 1 output buffer z o = 50 ? 1.5v for 3,3v i/o v ccq /2v for 2.5v i/o 50 ? ac test loads www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 13 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? read/write cycle switching characteristics (over operating range) -150 -133 symbol parameter min. max. min. max. unit f max clock frequency ? 150 ? 133 mhz t kc cycle time 6.7 ? 7.5 ? ns t kh clock high pulse width 2.5 ? 2.8 ? ns t kl clock low pulse width 2.5 ? 2.8 ? ns t kq clock access time ? 3.8 ? 4ns t kqx (1) clock high to output invalid 1.5 ? 1.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z ? 3.8 ? 4ns t oeq output enable to output valid ? 3.8 ? 4ns t oelz (1,2) output enable to output low-z 0 ? 0 ? ns t oehz (1,2) output enable to output high-z ? 3.8 ? 4ns t as address setup time 1.5 ? 1.5 ? ns t ss address status setup time 1.5 ? 1.5 ? ns t ws write setup time 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. www.datasheet.in
14 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? write cycle switching characteristics (over operating range) -150 -133 symbol parameter min. max. min. max. unit t kc cycle time 6.7 ? 7.5 ? ns t kh clock high pulse width 2.5 ? 2.8 ? ns t kl clock low pulse width 2.5 ? 2.8 ? ns t as address setup time 1.5 ? 1.5 ? ns t ss address status setup time 1.5 ? 1.5 ? ns t ws write setup time 1.5 ? 1.5 ? ns t ds data in setup time 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t dh data in hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns snooze mode electrical characteristics symbol parameter conditions min. max. unit i sb 2 current during snooze mode zz vih ? 15 ma t pds zz active to input ignored ? 2 cycle t pus zz inactive to input sampled 2 ? cycle t zzi zz active to snooze current ? 2 cycle t rzzi zz inactive to exit snooze current 0 ? ns www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 15 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b www.datasheet.in
16 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? write cycle timing single write data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2a 2b www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 17 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z www.datasheet.in
18 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? par par par par par t t t t t identifica identifica identifica identifica identifica tion tion tion tion tion 61xpsxxxxxx-xxxxxx rating commercial i - industrial package tq - tqfp b - pbga speed 150 - 150 mhz 133 - 133 mhz density 25632 - 256k x 32 25636 - 256k x 36 51218 - 512k x 18 s - single-cycle deselect d - double-cycle dedelect sp - 3.3v i/o synchronous pipeline lp - 2.5v i/o synchronous pipeline t - three chip selects d - two chip selects www.datasheet.in
integrated silicon solution, inc. ? 1-800-379-4774 19 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? commercial range: 0 c to +70 c speed order part number package 150 mhz is61sps51218t-150tq tqfp is61sps51218d-150tq tqfp is61sps51218d-150b pbga 133 mhz is61sps51218t-133tq tqfp is61sps51218d-133tq tqfp is61sps51218d-133b pbga industrial range: ? 40 c to +85 c speed order part number package 150 mhz is61sps51218t-150tqi tqfp is61sps51218d-150tqi tqfp 133 mhz is61sps51218t-133tqi tqfp is61sps51218d-133tqi tqfp ordering information commercial range: 0 c to +70 c speed order part number package 150 mhz is61sps25632t-150tq tqfp IS61SPS25632D-150tq tqfp IS61SPS25632D-150b pbga 133 mhz is61sps25632t-133tq tqfp IS61SPS25632D-133tq tqfp IS61SPS25632D-133b pbga industrial range: ? 40 c to +85 c speed order part number package 150 mhz is61sps25632t-150tqi tqfp IS61SPS25632D-150tqi tqfp 133 mhz is61sps25632t-133tqi tqfp IS61SPS25632D-133tqi tqfp commercial range: 0 c to +70 c speed order part number package 150 mhz is61sps25636t-150tq tqfp is61sps25636d-150tq tqfp is61sps25636d-150b pbga 133 mhz is61sps25636t-133tq tqfp is61sps25636d-133tq tqfp is61sps25636d-133b pbga industrial range: ? 40 c to +85 c speed order part number package 150 mhz is61sps25636t-150tqi tqfp is61sps25636d-150tqi tqfp 133 mhz is61sps25636t-133tqi tqfp is61sps25636d-133tqi tqfp www.datasheet.in
20 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 05/09/01 is61sps25632t/d is61lps25632t/d is61sps25636t/d is61lps25636t/d is61sps51218t/d is61lps51218t/d issi ? issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com commercial range: 0 c to +70 c speed order part number package 150 mhz is61lps51218t-150tq tqfp is61lps51218d-150tq tqfp is61lps51218d-150b pbga 133 mhz is61lps51218t-133tq tqfp is61lps51218d-133tq tqfp is61lps51218d-133b pbga industrial range: ? 40 c to +85 c speed order part number package 133 mhz is61lps51218t-133tqi tqfp is61lps51218d-133tqi tqfp ordering information commercial range: 0 c to +70 c speed order part number package 150 mhz is61lps25632t-150tq tqfp is61lps25632d-150tq tqfp is61lps25632d-150b pbga 133 mhz is61lps25632t-133tq tqfp is61lps25632d-133tq tqfp is61lps25632d-133b pbga industrial range: ? 40 c to +85 c speed order part number package 133 mhz is61lps25632t-133tqi tqfp is61lps25632d-133tqi tqfp commercial range: 0 c to +70 c speed order part number package 150 mhz is61lps25636t-150tq tqfp is61lps25636d-150tq tqfp is61lps25636d-150b pbga 133 mhz is61lps25636t-133tq tqfp is61lps25636d-133tq tqfp is61lps25636d-133b pbga industrial range: ? 40 c to +85 c speed order part number package 133 mhz is61lps25636t-133tqi tqfp is61lps25636d-133tqi tqfp www.datasheet.in

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